1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory device with a row redundancy circuit and method for using same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited to an xe2x80x9cfxe2x80x9d state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
FIG. 4 is a block diagram showing the related art nonvolatile ferroelectric memory device, FIG. 5 is a schematic diagram showing a unit of the related art nonvolatile ferroelectric memory device, and FIG. 6 is a diagram that shows partial detail of FIG. 5.
A driving circuit of the related art nonvolatile ferroelectric memory device will now be described with reference to FIGS. 4-6.
As shown in FIG. 5, the related art nonvolatile ferroelectric memory is provided with a main wordline driver 1, a first cell array 2 on one side of the main wordline driver 1, a first local wordline driver 3 on one side of the first cell array 2, a second local wordline driver 4 on one side of the first local wordline driver 3 and a second cell array 5 on one side of the second local wordline driver 4. A first local X decoder 6 is formed over the first local wordline driver 3, and a second local X decoder 7 is formed over the second local wordline driver 4. The first local wordline driver 3 is adapted to receive a signal from the main wordline driver 1 and a signal from the first local X decoder 6 and selects a wordline for the first cell array unit 2. The second local wordline driver 4 is adapted to receive a signal from the main wordline driver 1 and a signal from the second local X decoder 7 and selects a wordline for the second cell array 5. The related art nonvolatile ferroelectric memory provides a signal from the main wordline driver 1 both to the first and second local wordline drivers 3 and 4. Therefore, one of the first and second cell arrays 2 and 5 is selected depending on signals from the first local X decoder 5 and the second local X decoder 6. That is, either the first cell array 2 or the second cell array 5 is selected, and a wordline of the selected cell array is driven depending on signals from the first and second local X decoders 6 and 7.
FIG. 6 is a diagram that illustrates selection of one of the cell arrays depending on signals from the first and second local X decoders 6, 7 of FIG. 5. As shown in FIG. 6, the main wordline connected to the main wordline driver 1 is formed across the first and second local wordline drivers 3 and 4 and the first and second cell arrays 2 and 5. The first local wordline driver 3 is a NAND logic gate 8a for subjecting a signal from the main wordline driver 1 received through the main wordline and a signal from the first local X decoder 6 to an logical operation. An output of the logic gate 8a and logic gate 8b, which is also a NAND gate, is dependent on signals from the first and second local X decoders 6 and 7 regardless of the signal provided from the main wordline driver 1. For example, if it is assumed that a high signal is provided from the main wordline driver 1, the first cell array 2 is selected if a signal from the first local X decoder 6 is low and a signal from the second local X decoder 7 is high. Opposite to this, if a signal from the first local X decoder 6 is high and a signal from the second local X decoder 7 is low, the second cell array 5 is selected. Thus, selection of either of the first and second cell arrays is dependent on the signals from the first and second local X decoders 6 and 7. As described above, the circuits for driving a nonvolatile ferroelectric memory shown in FIGS. 5-6 are limited repeatable portions. Thus, there are a plurality of first and second local wordline drivers 3 and 4, the first and second cell arrays 2 and 5, and first and second local X decoders 6 and 7 in the related art nonvolatile ferroelectric memory of FIG. 4.
In the related art nonvolatile ferroelectric memory device of FIG. 4, when the row address fails, the main wordline driver 1, the first local X decoder 6 and the second local X decoder 7 are all driven to relieve the failed address.
As described above, the related art nonvolatile ferroelectric memory device has various disadvantages. First, when the row address fails, it is necessary to drive a main wordline driver, a first local X decoder and a second local X decoder at the same time so as to relieve the failed address, which reduces relief efficiency. Since the local X decoders corresponding to the first and second local wordline drivers are required, the memory requires a large area. The two local X decoders required for selection of either one of the left or right cell array occupy a large area. Such an area increase, even if the area should become smaller according to the trend of high density device packing, causes delays that drop an access speed and deteriorate a driving performance. Further, an increase in chip size is not favorable for device packing or cost.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device with a row redundancy circuit and method for relieving a failed address thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device with a row redundancy circuit and method for relieving a failed address thereof having a reduced layout.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device with a row redundancy circuit and method for relieving a failed address thereof that only uses a row redundancy circuit and a single local decoder when a main cell address fails.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device with a row redundancy circuit and method for relieving a failed address thereof, suitable for efficient relief of a row address failed in a main cell area and for efficient layout of a relieving circuit.
To achieve at least these objects and other advantages in a whole or in part and in accordance with purposes of the present invention, as embodied and broadly described, a nonvolatile ferroelectric memory device with a row redundancy circuit according to the present invention includes a main cell area having first and second cell array portions each with a plurality of cell arrays, and first and second local wordline drivers arranged between the first and second cell array portions to output a driving signal for any one of cells of the first and second cell array portions, a main wordline driver that outputs a control signal to activate any one of the first and second local wordline drivers of the main cell area, a redundancy cell area having first and second redundancy cell array portions for relieving errors generated when a row address of the main cell area is selected and first and second redundancy local wordline drivers, a row redundancy driving circuit that outputs an inactive signal to the main wordline driver when errors are generated in selecting the row address of the main cell area and outputs a control signal to the first and second redundancy local wordline drivers of the redundancy cell area and a local decoder that applies the driving signal to one of the first and second local wordline drivers of the main cell area and the redundancy cell area corresponding to first and second split wordlines of a selected cell of the main cell area and the redundancy cell area.
To further achieve the above objects in a whole or in parts, and in accordance with purposes of the present invention, there is provided a nonvolatile ferroelectric memory device that includes a main cell array including first and second memory arrays each having a plurality of cell arrays, first and second local wordline drivers between the first and second memory arrays that respectively output a driving signal for cells of the first and second memory arrays, a main wordline driver that provides a main control signal to activate one of the first and second local wordline drivers, a redundancy cell array including first and second redundancy memory arrays each having a plurality of cell arrays, wherein the redundancy cell array corrects an error generated when a row address of the main cell array is selected, first and second redundancy local wordline drivers that respectively output the driving signal for cells in the first and second redundancy memory arrays, a row redundancy driving circuit that provides an inactive signal to the main wordline driver when the error is generated for the selected the row address of the main cell array and a redundancy control signal to the first and second redundancy local wordline drivers, and a decoder that provides the driving signal corresponding to any cell of the main cell array and the redundancy cell array to one of the first and second local wordline drivers of the main cell array and the first and second redundancy local wordline drivers of the redundancy cell array.
To further achieve the above objects in a whole or in parts, and in accordance with purposes of the present invention, there is provided a row redundancy circuit for a memory device that includes a failed address coder that codes a failed address in a main cell area to generate a correction signal, a detector that detects the correction signal generated by the failed address coder to output a redundant address signal, an active signal generator that generates a redundant control signal in first and second redundancy local wordline drivers of a redundancy cell area responsive to the redundant address signal, and an inactive signal generator that provides an inactive signal for the main cell array responsive to the redundant address signal.
To further achieve the above objects in a whole or in parts, and in accordance with purposes of the present invention, there is provided a method for relieving a failed address of a nonvolatile ferroelectric memory device with a row redundancy circuit, wherein the nonvolatile ferroelectric memory has a main cell array and a redundant cell array that includes performing chip test after a wafer fabrication process, detecting a failed address of a main cell array, generating a relief address active signal by disabling an address fuse so that a failed address coder codes a corresponding address responsive to the failed address, detecting the relief address active signal and transmitting a relief address signal to a corresponding active signal generator and inactive signal generator, generating a redundant control signal for activating first and second local wordline drivers of the redundancy cell array from the relief address signal so as to activate a redundant split wordline driver and generating a driving signal in the first and second local wordline drivers of the redundancy cell area and at the same time generating an inactive signal for the main cell array.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.